The present invention relates to a memory cell with a stored charge on its gate, a kind of so-called DRAM gain cell.
A DRAM cell is composed of one transistor and one capacitor which can generally accomplish the minimum area among conventional RAM cells. With a design rule being finer, however, it is requested to develop a complicated capacitor structure and a new capacitor material for achieving a small area and a capacitance which a capacitor is required to have. And, the cost of DRAM production is increasing due to the formation and processing of dielectric materials and electrode films, researches and developments of passivation techniques and introduction of novel manufacturing apparatus, and the cost of the capacitor production is now much more expensive than that of the transistor production. Readout signals lessen as a finer semiconductor device is structured, and it is ultimately difficult to detect information stored in a memory cell without a change in structure and materials.
For overcoming the above problem, one DRAM gain cell is known in xe2x80x9cSuper-Low-Voltage Operation of a Semi-Static Complementary Gain DRAM Memory Cellxe2x80x9d, S. Shukuri, et al., 1993 Symposium on VLSI Technology, Digest of Tech. Papers, 3A-4, pp 23-24, 1993. FIG. 28 shows an equivalent circuit of the above DRAM gain cell composed of a memory transistor RM having a floating gate and a complementary word transistor WM. In the DRAM gain cell, a gate of the word transistor WM and a gate of the memory transistor RM are connected to a common word line WL, and one source/drain region of the word transistor WM and one source/drain region of the memory transistor RM are connected to a common bit line BL, so that the number of external wiring is decreased. When information is written in the above DRAM gain cell, a voltage, for example, of 1.5 volts is applied to the bit line BL, and a minus voltage is applied to the word line WL. As a result, a positive charge is stored on the floating gate of the memory transistor RM, and a gate threshold voltage of the memory transistor RM shifts toward a minus direction. When the DRAM gain cell is in a standby state, a potential is applied to the word line WL such that the memory transistor RM and the word transistor WM are not brought into an on-state. When information is read out, applied to the word line WL is a potential between the gate threshold voltage of the memory transistor RM when a positive charge is stored on the floating gate and the gate threshold voltage when no positive charge is stored. As a result, when a positive charge is stored on the floating gate, a current flows through the DRAM gain cell.
As explained above, the DRAM gain cell shown in FIG. 28 in principle requires no capacitor although it is required as an auxiliary in some cases. However, when it is attempted to decrease the area of the DRAM gain cell, the word transistor WM is required to be composed of a thin film transistor (TFT), and the problem is that the production process is complicated and that the DRAM gain cell can be no longer produced by a conventional production process. Further, there is another problem that controllability and reproducibility of TFTs are difficult when mass production technologies available at present are applied. Moreover, there is still another problem that since the above DRAM gain cell has a small operation margin, it is required to connect the gates or the drains of the two transistors to different word lines or different bit lines for securing the operation margin, and that the area of such a DRAM gain cell cannot be decreased.
It is therefore an object of the present invention to provide a memory cell with a stored charge on its gate, which does not require much complicated production process, which serves to suppress an increase in the number of external wiring and the area of a terminal portion, which can be produced almost equally by applying a process of producing a conventional flash memory, which does not require complicatedly structured capacitor unlike a conventional DRAMSand which can suppress an increase in a cell area.
The memory cell with a stored charge on its gate, provided by the present invention, for achieving the above object is a memory cell comprising;
(A) a channel-forming region,
(B) a first gate formed on an insulation layer formed on the surface of the channel-forming region, the first gate and the channel-forming region facing each other through the insulation layer,
(C) a second gate capacitively coupled with the first gate,
(D) source/drain regions formed in contact with the channel-forming region, one source/drain region being spaced from the other,
(E) a first non-linear resistance element having two ends, one end being connected to the first gate, and
(F) a second non-linear resistance element composed of the first gate, the insulation layer and either the channel-forming region and at least one of the source/drain regions.
In the above first non-linear resistance element, the xe2x80x9cone end connected to the first gatexe2x80x9d includes a case where said one end of the first non-linear resistance element has a common region with or serves as the first gate.
In the memory cell with a stored charge on its gate, provided by the present invention (to be simply referred to as xe2x80x9cmemory cellxe2x80x9d hereinafter), the insulation layer has a thickness which permits the flow of tunneling current in the insulation layer when a proper potential is applied between the first gate and the channel forming region or at least one of the source/drain regions which constitutes the second non-linear resistance element. The insulation layer can be formed of SiO2, SiN, SiON, a laminated structure of SiO2/SiN or the like. Of these, SiO2 (silicon oxide layer) having a thickness of 3 nm or less is preferred for forming the insulation layer. The second non-linear resistance element preferably comprises a so-called MIS (Metal-Insulator-Semiconductor) type or MOS (Metal-Oxide-Semiconductor) type tunnel diode which is composed of the first gate, the insulation layer and the channel forming region, of the first gate, the insulation layer and one of the source/drain regions, of the first gate, the insulation layer and both of the source/drain regions; of the first gate, the insulation layer, the channel forming region and one of the source/drain regions or of the first gate, the insulation layer, the channel forming region and both of the source/drain regions.
In the memory cell of the present invention, the first non-linear resistance element preferably has a two-terminal operation characteristic. The term xe2x80x9ctwo-terminal operation characteristicxe2x80x9d refers to an operation characteristic that the amount of current which flows between two regions is uniquely determined depending upon a voltage between the two regions as in a diode.
In the memory cell of the present invention, preferably, the first non-linear resistance element has characteristics that it is brought into a low resistive state when a first voltage having the same polarity as that of a forward conduction voltage and having an absolute value which is equal to, or greater than, an absolute value of the forward conduction voltage is applied across the two ends and that it is brought into a high resistive state when a second voltage having the same polarity as that of the forward conduction voltage and having an absolute value smaller than the absolute value of the forward conduction voltage or a voltage having an opposite polarity to the forward conduction voltage is applied across the two ends. For example, when the first non-linear resistance element comprises a diode, it is preferred to use a diode having characteristics that it is brought into a low resistive state when the first voltage equal to, or higher than, the forward conduction voltage is applied.
Specifically, as the first non-linear resistance element having the above characteristics, a pn junction diode can be used. In this case, preferably, the pn junction diode has a semiconductor region which is the same as the source/drain regions in conductivity type and a semiconductor region which is opposite to the source/drain regions in conductivity type, the semiconductor region which is opposite to the source/drain regions in conductivity type corresponds to said one end of the first non-linear resistance element, and the semiconductor region which is the same as the source/drain regions in conductivity type corresponds to said other end of the first non-linear resistance element. The pn-junction diode preferably has a pn junction region formed of a single crystal semiconductor, for achieving a higher resistance value of the first non-linear resistance element in a high resistive state. Otherwise, the pn junction diode preferably has a lateral pn junction in view of the fact that the resistance value of the first non-linear resistance element in a high resistive state can be further increased. Further, the first non-linear resistance lement may comprise a hetero-junction diode from the view point of decreasing (lowering) the forward conduction voltage.
In the memory cell of the present invention, the second gate can be capacitively coupled with the first gate through a dielectric film. The dielectric film can be formed, for example, of SiO2, SiO2/SixNy, SiO2/SixNy/SiO2 or Ta2O5/SixNy.
The memory cell of the present invention, may have a configuration in which the second gate is connected to a word line, said other end of the first non-linear resistance element is connected to a bit line, one source/drain region is connected to a read line, and the channel-forming region or at least one of the source/drain regions which constitutes the second non-linear resistance element is connected to an erase line. The above memory cell of the present invention will be called xe2x80x9cmemory cell according to the first configuration of the present inventionxe2x80x9d. The read line may be formed in parallel with the word line or may be formed in parallel with the bit line. That is, there may be employed a constitution in which a plurality of the memory cells are connected to one word line and one read line or a plurality of the memory cells are connected to one bit line and one read line. Further, there may be employed a constitution in which the memory cells in an arbitrary number, disposed in an arbitrary position, are connected with one read line. Further, preferably, the erase line is connected to a plurality of the memory cells.
In the memory cell according to the first configuration of the present invention, preferably, a first bit-line potential is applied to the bit line, a first read-line potential is applied to the read line and then a word-line potential is switched from a first word-line potential to a second word-line potential, thereby to generate the first voltage between the first gate and said other end of the first non-linear resistance element through the capacitive coupling between the first gate and the second gate and to bring the first non-linear resistance element into a low resistive state, whereby a charge of a first polarity is transported from the bit line to the first gate through the first non-linear resistance element and the charge of the first polarity is stored on or in the first gate. In this manner, information is written in the memory cell.
In the memory cell according to the first configuration of the present invention, preferably, a second bit-line potential is applied to the bit line, a first read-line potential is applied to the read line and then a word-line potential is switched from a first word-line potential to a second word-line potential, thereby to generate the second voltage or a voltage having an opposite polarity to the forward conduction voltage between the first gate and said other end of the first non-linear resistance element through the capacitive coupling between the first gate and the second gate and to keep the first non-linear resistance element in a high resistive state, whereby the charge stored on or in the first gate is prevented from undergoing a change in state. In this manner, writing information in the memory cell can be inhibited.
In the memory cell according to the first configuration of the present invention, preferably, an erase-line potential is applied to the erase line to transport a charge having a second polarity opposite to the first polarity from the erase line to the first gate through the second non-linear resistance element, or to discharge the charge having the first polarity from the first gate to the erase line through the second non-linear resistance element, whereby the charge storage state of the first gate is brought into a second charge storage state. In this manner, information stored in the memory cell can be erased.
In the memory cell according to the first configuration of the present invention, preferably, the first non-linear resistance element comprises a pn junction diode and is formed in the first gate or formed in or on an extended region of the first gate, for the view point of simplifying the constitution. The above pn junction diode can have a semiconductor region which is the same as the source/drain regions in conductivity type and a semiconductor region which is opposite to the source/drain regions in conductivity type, the semiconductor region which is opposite to the source/drain regions in conductivity type corresponds to said one end of the first non-linear resistance element, and the semiconductor region which is the same as the source/drain regions in conductivity type corresponds to said other end of the first non-linear resistance element.
When the first gate or the extended region of the first gate is formed of a polysilicon film, the above pn junction diode may be constituted so as to have a lateral pn junction formed in the polysilicon film. Further, preferably, polysilicon is single-crystallized, and at least the pn junction region is formed in a single-crystallized portion, i.e., the pn junction region of the pn junction diode is formed of a single crystal semiconductor, in view of the fact that the resistance value of the first non-linear resistance element in a high resistive state can be further increased.
Alternatively, in the memory cell according to the first configuration of the present invention, preferably, the first non-linear resistance element comprises a hetero-junction diode and is formed on the first gate or on an extended region of the first gate, from the view point of decreasing (lowering) the forward conduction voltage.
The memory cell, provided by the present invention preferably, may have a configuration in which the second gate is connected to a word line, said other end of the first non-linear resistance element and one source/drain region are connected to a bit line, and the channel-forming region or at least one of the source/drain regions which constitutes the second non-linear resistance element is connected to an erase line. The above memory cell of the present invention will be called xe2x80x9cmemory cell according to the second configuration of the present inventionxe2x80x9d.
In the memory cell according to the second configuration of the present invention, preferably, a first bit-line potential is applied to the bit line and then a word-line potential is switched from a first word-line potential to a second word-line potential, thereby to generate the first voltage between the first gate and said other end of the first non-linear resistance element through the capacitive coupling between the first gate and the second gate and to bring the first non-linear resistance element into a low resistive state, whereby a charge of a first polarity is transported from the bit line to the first gate through the first non-linear resistance element and the charge of the first polarity is stored on or in the first gate. In this manner, information can be written in the memory cell.
In the memory cell according to the second configuration of the present invention, preferably, a second bit-line potential is applied to the bit line and then a word-line potential is switched from a first word-line potential to a second word-line potential, thereby to generate the second voltage or a voltage having an opposite polarity to the forward conduction voltage, between the first gate and said other end of the first non-linear resistance element through the capacitive coupling between the first gate and the second gate and to keep the first non-linear resistance element in a high resistive state, whereby the charge stored on or in the first gate is prevented from undergoing a change in state. In this manner, writing information in the memory cell can be inhibited.
In the memory cell according to the second configuration of the present invention, preferably, similarly, an erase-line potential is applied to the erase line to transport a charge having a second polarity opposite to the first polarity from the erase line to the first gate through the second non-linear resistance element, or to discharge the charge having the first polarity from the first gate to the erase line through the second non-linear resistance element, whereby the charge storage state of the first gate is brought into a second charge storage state. In this manner, information stored in the memory cell can be erased.
In the memory cell according to the second configuration of the present invention, preferably, the first non-linear resistance element comprises a pn junction diode and is formed in the first gate or formed in or on an extended region of the first gate, from the view point of simplifying the constitution. Preferably, the above pn junction diode has a semiconductor region which is the same as the source/drain regions in conductivity type and a semiconductor region which is opposite to the source/drain regions in conductivity type, the semiconductor region which is opposite to the source/drain regions in conductivity type corresponds to said one end of the first non-linear resistance element, and the semiconductor region which is the same as the source/drain regions in conductivity type corresponds to said other end of the first non-linear resistance element.
When the first gate or the extended region of the first gate is formed of a polysilicon film, the above pn junction diode may be constituted so as to have a lateral pn junction formed in the polysilicon film. Further, preferably, polysilicon is single-crystallized, and at least the pn junction region is formed in a single-crystallized portion, i.e., the pn junction region of the pn junction diode is formed of a single crystal semiconductor, in view of the fact that the resistance value of the first non-linear resistance element in a high resistive state can be further increased. Otherwise, preferably, the first non-linear resistance element comprises a hetero-junction diode and is formed on the first gate or on an extended region of the first gate, from the view point of decreasing (lowering) the forward conduction voltage.
The memory cell, provided by the present invention, preferably has a configuration in which the second gate is connected to a word line, said other end of the first non-linear resistance element is connected to one source/drain region, said one source/drain region is connected to a bit line, and the channel forming region or at least one of the source/drain regions which constitutes the second non-linear resistance element is connected to an erase line. The above memory cell will be called xe2x80x9cmemory cell according to the third configuration of the present inventionxe2x80x9d. The above expression xe2x80x9cthe other end of the first non-linear resistance element is connected to one source/drain regionxe2x80x9d includes a case where said other end of the first non-linear resistance element has a common region with or serves as said one source/drain region. When the second non-linear resistance element comprises at least one of the source/drain regions, said one of the source/drain regions is to be different from one source/drain region to which said other end of the first non-linear resistance element is connected.
In the memory cell according to the third configuration of the present invention, preferably, a first bit-line potential is applied to the bit line and then a word-line potential is switched from a first word-line potential to a second word-line potential, thereby to generate the first voltage between the first gate and said one source/drain region through the capacitive coupling between the first gate and the second gate and to bring the first non-linear resistance element into a low resistive state, whereby a charge of a first polarity is transported from the bit line to the first gate through said one source/drain region and the first non-linear resistance element, and the charge of the first polarity is stored on or in the first gate. In this manner, information can be written in the memory cell.
In the memory cell according to the third configuration of the present invention, preferably, a second bit-line potential is applied to the bit line and then a word-line potential is switched from a first word-line potential to a second word-line potential, thereby to generate the second voltage or a voltage having an opposite polarity to the forward conduction voltage, between the first gate and said one source/drain region through the capacitive coupling between the first gate and the second gate and to keep the first non-linear resistance element in a high resistive state, whereby the charge stored on or in the first gate is prevented from undergoing a change in state. In this manner, writing information in the memory cell can be inhibited.
In the memory cell according to the third configuration of the present invention as well, preferably, an erase-line potential is applied to the erase line to transport a charge having a second polarity opposite to the first polarity from the erase line to the first gate through the second non-linear resistance element, or to discharge the charge having the first polarity from the first gate to the erase line through the second non-linear resistance element, whereby the charge storage state of the first gate is brought into a second charge storage state. In this manner, information stored in the memory cell can be erased.
The memory cell according to the third configuration of the present invention may have a configuration in which the first non-linear resistance element comprises a pn junction diode, one region of the pn junction diode (a region of the pn junction diode which is opposite to the source/drain regions in conductivity type) corresponding to said one end of the first non-linear resistance element is formed in said one source/drain region, and the other region of the pn junction diode (a region of the pn junction diode which is the same as the source/drain regions in conductivity type) corresponding to said other end of the first non-linear resistance element has a common region with or serves as said one source/drain region. Otherwise, it may have a configuration in which the first non-linear resistance element preferably comprises a pn junction diode, one region of the pn junction diode (a region of the pn junction diode which is opposite to the source/drain regions in conductivity type) corresponding to said one end of the first non-linear resistance element has a common region with or serves as the first gate, and the other region of the pn junction diode (a region of the pn junction diode which is the same as the source/drain regions in conductivity type) corresponding to said other end of the first non-linear resistance element is formed in an extended region of the first gate extending to said one source/drain region. When the first gate or the extended region of the first gate is formed of a polysilicon, the above pn junction diode may be constituted so as to have a lateral pn junction formed in the polysilicon film. Further, preferably, polysilicon is single-crystallized, and at least the pn junction region is formed in a single-crystallized portion, i.e., the first non-linear resistance element comprises a pn junction diode and the pn junction region of the pn junction diode is formed of a single crystal semiconductor, in view of the fact that the resistance value of the first non-linear resistance element in a high resistive state can be further increased. Otherwise, preferably, the pn junction diode constituting the first non-linear resistance element has a lateral pn junction, in view of the fact that the resistance value of the first non-linear resistance element in a high resistive state can be further increased. Otherwise, preferably, the first non-linear resistance element comprises a hetero-junction diode from the view point of decreasing (lowering) the forward conduction voltage.
In the memory cells according to the first, second or third configuration of the present invention, preferably, the other source/drain region is reversely biased with regard to the channel forming region when the second word-line potential is applied to the word line. Specifically, when the memory cell is n type, a potential greater than a value obtained by deducting a gate threshold voltage (seen from the first gate) from a potential of the first gate can be applied to said other source/drain region, and when the memory cell is p type, a potential smaller than a value obtained by deducting a gate threshold voltage (seen from the first gate) from a potential of the first gate can be applied to said other source/drain region. Alternatively, preferably, the other source/drain region is brought into a floating state with regard to the channel forming region when the second word-line potential is applied to the word line. Specifically, for example, a transistor for selection connected to said other source/drain region can be turned off. In the above manner, the current which flows between the source/drain regions of the memory cell can be reliably inhibited when information is written, i.e., when a charge is stored on or in the first gate, and the power consumption of the memory cell can be decreased.
In the memory cells according to the first, second or third configuration of the present invention, there may be employed an embodiment in which the charge to be stored on or in the first gate can correspond to stored information and the stored information is information corresponding to a level number of the first bit-line potential. In this case, there may be employed an embodiment in which the level number of the first bit-line potential to be applied to the bit line is one and the stored information is binary information, and there may be also employed another embodiment in which the level number of the first bit-line potential to be applied to the bit line is at least two and the stored information is multi-valued information.
Otherwise, there may be employed an embodiment in which the charge to be stored on or in the first gate corresponds to stored information and the stored information is information corresponding to a level number of the second word-line potential. In this case, there may be employed an embodiment in which the level number of the second word-line potential to be applied to the word line is one and the stored information is binary information, and there may be also employed another embodiment in which the level number of the second word-line potential to be applied to the word line is at least two and the stored information is multi-valued information.
Further, there may be employed an embodiment in which the charge to be stored on or in the first gate corresponds to stored information and the stored information is information corresponding to a level number of the voltage between the second word-line potential and the first bit-line potential. In this case, there may be employed an embodiment in which the level number of the voltage between the second word-line potential and the first bit-line potential is one and the stored information is binary information, and there may be also employed another embodiment in which the level number of the voltage between the second word-line potential and the first bit-line potential is at least two and the stored information is multi-valued information.
For example, when the first bit-line potential applied to the bit line has a level number of two, or when the second word-line potential applied to the word line has a level number of two, or further, when the voltage between the second word-line potential and the first bit-line potential has a level number of two, stored information is ternary information. For example, when the first bit-line potential applied to the bit line has a level number of three, or when the second word-line potential applied to the word line has a level number of three, or further, when the voltage between the second word-line potential and the first bit-line potential has a level number of three, stored information is 4-valued information. Generally, when the first bit-line potential applied to the bit line has a level number of M, or when the second word-line potential applied to the word line has a level number of M, or further, when the voltage between the second word-line potential and the first bit-line potential has a level number of M, stored information is (M+1)-valued information.